Because compiling projects can be such a complicated and repetitive
process, a good IDE provides a means to abstract, simplify, and even
automate software builds. Unix and its descendents accomplish this
process with a
Makefile, a prescribed recipe in a standard
format for generating executable files from source and object files,
taking account of changes to only rebuild
what’s necessary to prevent
costly recompilation.
Anatomy of a Makefile
Makefile is a list of variables and a list of targets,
and the sources and/or objects used to provide them. Targets may not
necessarily be linked binaries; they could also constitute actions to
perform using the generated files, such as install to instate built files into the system, and clean to remove built files from the source tree.It’s this flexibility of targets that enables
make to
automate any sort of task relevant to assembling a production build of
software; not just the typical parsing, preprocessing, compiling proper
and linking steps performed by the compiler, but also running tests (make test),
compiling documentation source files into one or more appropriate
formats, or automating deployment of code into production systems, for
example, uploading to a website via a git push or similar content-tracking method.An example
Makefile for a simple software project might look something like the below:CC=gcc
#The basic makefile is composed of:
#target: dependencies
#[tab] system command
hello.o: hello.c
$(CC) hello.c -o hello.o
install: hello.o
cp hello.o /bin
If you run
make
this program will look for a file named makefile in your directory, and then execute it.
If you have several makefiles, then you can execute them with the command:
make -f MyMakefile
